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1 ?2016 integrated device technology, inc june 28, 2016 general description the 87973i-147 is a lvcmos/lvttl clock generator. the 87973i-147 has three selectable inputs and provides 14 lvcmos/lvttl outputs. the 87973i-147 is a highly flexible device. the three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock so urces. up to three different output frequencies can be gener ated among the three output banks. the three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. in addition, 2 outputs in bank c (q c2, qc3) can be selected to be inverting or non-inverting. the output frequency range is 10mhz to 150mhz. the input frequency range is 6mhz to 120mhz. the 87973i-147 also has a qsync output which can be used for system synchronization purposes. it monitors bank a and bank c outputs and goes low one period prior to coincident rising edges of bank a and bank c clocks. qsy nc then goes high again when the coincident rising edges of bank a and bank c occur. this feature is used primarily in applications wher e bank a and bank c are running at different frequencies, and is pa rticularly useful when they are running at non-integer multiples of one another. example applications: 1. system clock generator: use a 16.66mhz reference clock to generate eight 33.33mhz copies for pci and four 100mhz copies for the cpu or pci-x. 2. line card multiplier: multiply differential 62.5mhz from a back plane to single-ended 125mhz for the line card asics and gigabit ethernet serdes. 3. zero delay buffer for synchronous memory: fanout up to twelve 100mhz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. features ? fully integrated pll ? fourteen lvcmos/lvttl outputs to include: twelve clocks, one feedback, one sync ? selectable differential clk, nclk inputs or lvcmos/lvttl reference clock inputs ? clk0, clk1 can accept the following input levels: lvcmos or lvttl ? clk, nclk pair can accept the following differential input levels: lvpecl, lv ds, lvhstl, sstl, hcsl ? output frequency range: 10mhz to 150mhz ? vco range: 240mhz to 500mhz ? output skew: 200ps (maximum) ? cycle-to-cycle jitter, (all banks 4) : 55ps (maximum) ? full 3.3v supply voltage ? -40c to 85c ambient operating temperature ? compatible with powerpc? and pentium? microprocessors ? available in lead-free packages ? for drop-in replacement use 87973i pin assignment 52-lead, 10mm x 10mm lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 40 41 42 43 44 45 46 47 48 49 50 51 52 21 22 23 24 25 26 20 19 18 17 16 15 14 32 33 34 35 36 37 38 39 31 30 29 28 27 fsel_b1 fsel_b0 fsel_a1 fsel_a0 qa3 v ddo qa2 gndo qa1 v ddo qa0 gndo vco_sel fsel_fb1 qsync gndo qc0 v ddo inv_clk qc1 fsel_c0 fsel_c1 qc2 v ddo qc3 gndo gndi v dda nmr/oe frz_clk frz_data fsel_fb2 pll_sel ref_sel clk_sel clk0 clk1 clk nclk gndo qb0 v ddo qb1 gndo qb2 v ddo qb3 fsel_fb0 ext_fb gndo qfb v dd 87973i-147 product discontinuation notice - la st time buy expires may 6, 2017 87973i-147 data sheet low skew, 1-to-1 2 lvcmos/ lvttl clock multiplier/ zero delay buffer
2 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet block diagram s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz qa0 qa1 qa2 qa 3 qb0 qb1 qb2 qb 3 qc0 qc1 qc2 qc 3 qfb q s ync clk nclk vco_ s el pll_ s el ref_ s el ext_fb clk0 clk1 p u ll u p p u ll u p p u ll u p pu/pd p u ll u p p u ll u p p u ll u p clk_ s el p u ll u p p u ll u p frz_clk p u ll u p p u ll u p p u ll u p p u ll u p p u ll u p p u ll u p frz_data p u ll u p inv_clk f s el_a[0:1] f s el_b[0:1] f s el_c[0:1] f s el_fb[0:2] f s el_fb2 nmr/oe p u ll u p 2 2 2 3
3 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet simplified block diagram 0 1 1 0 0 1 1 2 s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz s ync frz o utput d i s able c ircuitry 0 1 0 1 pll vco r ange 240mhz - 500mhz s ync frz 3 2 2 2 inv_clk f s el_a[0:1] f s el_b[0:1] f s el_c[0:1] f s el_fb[0:2] nmr/oe 0 0 4 0 1 6 1 0 8 1 1 12 fsel_ a1 a0 qax 0 0 4 0 1 6 1 0 8 1 1 10 fsel_ b1 b0 qbx 0 0 0 4 0 0 1 6 0 1 0 8 0 1 1 10 1 0 0 8 1 0 1 12 1 1 0 16 1 1 1 20 fsel_ fb2 fb1 fb0 qfb 0 0 2 0 1 4 1 0 6 1 1 8 fsel_ c1 c0 qcx clk nclk vco_ s el pll_ s el ref_ s el ext_fb clk0 clk1 p u ll u p p u ll u p p u ll u p pu/pd p u ll u p p u ll u p p u ll u p clk_ s el p u ll u p p u ll u p qa0 qa1 qa2 qa 3 qb0 qb1 qb2 qb 3 qc0 qc1 qc2 qc 3 qfb q s ync frz_clk p u ll u p frz_data p u ll u p p u ll u p
4 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet pin descriptions and pin characteristic tables table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1 gndi power power supply ground. 2 nmr/oe input pullup master reset and output enable. when high, enables the outputs. when low, resets the outputs in a high-impedance state and resets output divide circuitry. enables and disables all output s. lvcmos / lvttl interface levels. 3 frz_clk input pullup clock input for freeze ci rcuitry. lvcmos / lvttl interface levels. 4 frz_data input pullup configuration data input for fr eeze circuitry. lvcmos / lvttl interface levels. 5, 26, 27 fsel_fb2, fsel_fb1, fsel_fb0 input pullup select pins control feedback divide va lue. lvcmos / lvttl interface levels. see table 3b. 6 pll_sel input pullup selects between the pll and reference cloc ks as the input to the output dividers. when high, selects pll. when low, bypasses the pll and reference clocks. lvcmos / lvttl interface levels. 7 ref_sel input pullup selects between clk0 or clk1 and clk, nclk inputs. when low, selects clk0 or clk1. when high, clk, nclk inputs. lvcmos / lvttl interface levels. 8 clk_sel input pullup clock select input. when low, selects clk0. wh en high, selects clk1. lvcmos / lvttl interface levels. 9, 10 clk0, clk1 input pullup single-ended reference clock inputs. lvcmos/lvttl interface levels. 11 clk input pullup non-inverting differential clock input. 12 nclk input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 13 v dda power analog supply pin. 14 inv_clk input pullup inverted clock select for qc2 a nd qc3 outputs. lvcmos / lvttl interface levels. 15, 24, 30, 35, 39, 47, 51 gndo power power supply ground. 16, 18, 21, 23 qc3, qc2, qc1, qc0 output single-ended bank c clock outputs. lvcmos/ lvttl interface levels. 17, 22, 33, 37, 45, 49 v ddo power output power supply pins. 19, 20 fsel_c1, fsel_c0 input pullup select pins for bank c outputs. lvcmos / lvttl interface levels. see table 3a. 25 qysnc output synchronization output for bank a and bank c. refer to figure 1, timing diagrams. lvcmos / lvttl interface levels. 28 v dd power power supply pin. 29 qfb output single-ended feedback clock outp ut. lvcmos / lvttl interface levels. 31 ext_fb input pullup external feedback. lvcmos / lvttl interface levels. 32, 34, 36, 38 qb3, qb2, qb1, qb0 output single-ended bank b clock output s. lvcmos/ lvttl interface levels. 40, 41 fsel_b1, fsel_b0 input pullup select pins for bank b outputs. lvcmos / lvttl interface levels. see table 3a. 42, 43 fsel_a1, fsel_a0 input pullup select pins for bank a outputs. lvcmos / lvttl interface levels. see table 3a. 44, 46 48, 50 qa3, qa2, qa1, qa0 output single-ended bank a clock output s. lvcmos/ lvttl interface levels. 52 vco_sel input pullup selects vco. when high, selects vco 1. when low, selects vco 2. lvcmos / lvttl interface levels.
5 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet table 2. pin characteristics function tables table 3a. output bank configuration select function table table 3b. feedback configuration select function table table 3c. control input select function table symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? c pd power dissipation capacitance (per output) v dd, v dda, v ddo = 3.465v 18 pf r out output impedance 5 7 12 ? inputs outputs inputs outputs inputs outputs fsel_a1 fsel_a0 qa fsel_b1 fse l_b0 qb fsel_c1 fsel_c0 qc 0 0 4 0 0 4 0 0 2 0 1 6 0 1 6 0 1 4 1 0 8 1 0 8 1 0 6 1 1 12 1 1 10 1 1 8 inputs outputs fsel_fb2 fsel_fb1 fsel_fb0 qfb 000 4 001 6 010 8 011 10 100 8 101 12 110 16 111 20 control pin logic 0 logic 1 vco_sel vco/2 vco ref_sel clk0 or clk1 xtal clk_sel clk0 clk1 pll_sel bypass pll enable pll nmr/oe master reset/output high-impedance enable outputs inv_clk non-inverted qc2, qc3 inverted qc2, qc3
6 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet figure 1. timing diagrams fvco qa qc qsync qa qa(4) qc qc(2) qsync qsync qa(8) qc(2) qsync qa(8) qc(2) qsync qc(8) qa(6) qsync qc(2) qa(12) qsync 1:1 mode 2:1 mode 3:2 mode 3:1 mode 4:1 mode 4:3 mode 6:1 mode
7 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications on ly. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = -40c to 85c table 4b. dc characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information section. load test circuit diagram. note 2: v il should not be less than -0.3v. note 3: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ? ja 42.3 ? c/w (0 lfpm) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 225 ma i dda analog supply current 20 ma symbol parameter test conditio ns minimum typic al maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i in input current 120 a v oh output high voltage; note 1 i oh = -20ma 2.4 v v ol output low voltage; note 1 i ol = 20ma 0.5 v v pp peak-to-peak input voltage; note 2, 3 clk, nclk 0.3 1 v v cmrp common mode input voltage; note 2, 3 clk, nclk v dd - 2 v dd - 0.6 v
8 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet table 5. input frequency characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = -40c to 85c note 1: input frequency depends on the feedback divide ratio to en sure "clock * feedback divide" is in the vco range of 240mhz to 500mhz. ac electrical characteristics table 6. ac characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient op erating temperature range, wh ich is established when th e device is mounted in a test socket with maintained transverse airflow grea ter than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: defined as the time difference bet ween the input reference clock and the aver age feedback input signal when the pll is locked and the input reference frequency is stable. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units f in input frequency clk0, clk1; note 1 120 mhz frz_clk 20 mhz symbol parameter test conditio ns minimum typi cal maximum units f out output frequency 2 250 mhz 4 125 mhz 6 83.33 mhz 8 62.5 mhz 10 50 mhz 12 41.66 mhz t(?) static phase offset; note 1 clk0 qfb 8, in frequency = 50mhz -10 145 300 ps clk1 -65 90 245 ps clk, nclk -130 18 165 ps t sk(o) output skew; note 2, 3 200 ps tjit(cc) cycle-to-cycle jitter; note 3 all banks 4 55 ps f vco pll vco lock range 240 500 mhz t lock pll lock time; note 4 10 ms t r / t f output rise/fall time 0.8v to 2v 150 700 ps odc output duty cycle 45 55 % t pzl, t pzh output enable time; note 4 10 ns t plzl, t phz output disable time; note 4 8ns
9 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet parameter measurement information lvcmos output load ac test circuit cycle-to-cycle jitter lvcmos static phase offset differential input level output skew differential static phase offset scope qx gnd v dd, 1.65v5% -1.65v5% v ddo v dda, ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles qa[0:3], qb[0:3], qc[0:3], qsync, qfb ? ? t (?) v dd 2 v dd 2 t (?) mean = static phase offset where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges clk0, clk1 ext_fb v cmr cross points v pp v dd gnd nclk clk t sk(o) qx qy t (?) ? ? v dd 2 v dd 2 t (?) mean = static phase offset where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges nclk ext_fb nclk
10 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet parameter measurement information, continued output duty cycle/pulse width period output rise/fall time application information recommendations for unu sed input and output pins inputs: clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. clk inputs for applications not requiring the use of the clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk to ground. lvcmos control pins all control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached. t period t pw t period odc = v ddo 2 x 100% t pw qa[0:3], qb[0:3], qc[0:3], qsync, qfb 0.8v 2v 2v 0.8v t r t f qa[0:3], qb[0:3], qc[0:3], qsync, qfb
11 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required . the 87973i-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 2 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 ? f bypass capacitor be connected to the v dda pin. figure 2. power supply filtering wiring the differential input to accept single-ended levels figure 3 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 3. recommended schematic for wiring a di fferential input to accept single-ended levels v dd v dda 3 . 3 v 10 f 0.1 f 0.1 f ferrite be a d
12 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4e show interface examples for the clk/nclk input dr iven by the most common driver types. the input interfaces s uggested here are examples only. please consult with the vendor of th e driver component to confirm the driver termination requirements. fo r example, in figure 4a, the input termination applies for idt open emit ter lvhstl drivers. if you are using an lvhstl driver from ano ther vendor, use their termination recommendation. figure 4a. clk/nclk input driven by an idt open emitter lvhstl driver figure 4c. clk/nclk input driven by a 3.3v lvpecl driver figure 4e. clk/nclk input driven by a 3.3v lvds driver figure 4b. clk/nclk input driven by a 3.3v lvpecl driver figure 4d. clk/nclk input driven by a 3.3v hcsl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t
13 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet using the output freeze circuitry o verview to enable low power states within a system, each output of 87973i-147 (except qc0 and qfb) can be individually frozen (stopped in the logic ?0? state) using a simple serial interface to a 12 bit shift register. a serial interface was chosen to eliminate the need for each output to have its own output enable pin, which would dramatically increase pin count and package cost. common sources in a system that can be used to drive the 87973i-147 serial interface are fpga?s and asics. p rotocol the serial interface consists of two pins, frz_data (freeze data) and frz_clk (freeze clock). each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. the sequence is started by supplying a logic ?0? start bit followed by 12nrz freeze enable bits. the period of each frz_data bit equals the period of the frz_clk signal. the frz_data serial transmission should be timed so the 87973i-147 can sample each frz_data bit with the rising edge of the frz_clk signal. to place an output in the freeze state, a logic ?0? must be written to the respective freeze enable bit in the shift register. to unfreeze an output, a logic ?1? must be written to the respective freeze enable bit. outputs will not become enabled/disabled until all 12 data bits are shifted into the shift register. when all 12 data bits are shifted in the register, the next rising edge of frz_clk will enable or disable the outputs. if the bit that is following the 12th bit in the register is a logic ?0?, it is used for the start bit of the next cycle; otherwise, the device will wait and won?t start the next cycle until it sees a logic ?0? bit. freezing and unfreezing of the output clock is synchronous (see the timing diagram below). when going into a frozen state, the output clock will go low at the time it would normally go low, and the freeze logic will keep the output low until unfrozen. likewise, when coming out of the frozen state, the output will go high only when it would normally go high. this logic, therefore, prevents runt pulses when going into and out of the frozen state. frz latched frz clocked qx f reeze internal qx internal qx out frz_clk frz_data start bit qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc1 qc2 qc3 q s ync figure 5. output disable timing diagram figure 5a. freeze data input protocol
14 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet schmatic example figure 6 shows a schematic example of using 87973i-147. this example shows general design of input, output termination, logic control input pull up/down and power supply filtering. in this example, the clock input is driven by an lvcmos driver. figure 6. 87973i-147 schematic layout vdd=3.3v (u1-17) (u1-22) (u1-28) (u1-33) (u1-37) (u1-45) (u1-49) set logic input to '0' to logic input pins to logic input pins logic input pin examples set logic input to '1' vdd vdd vdd serial clcok serial data vdd vdd vdd vdd zo = 50 rd1 not install r3 43 c16 10u lvcmos clock c8 0.1uf r6 1k r2 43 ru2 not install ru1 1k r7 fb rd2 1k rs r5 1k r9 1k r1 43 r8 1k c7 0.1uf zo = 50 r4 1k c11 0.01u zo = 50 c5 0.1uf r10 1k c9 0.1uf c3 0.1uf zo = 50 c4 0.1uf u1 ics87973i-147 gndi 1 nmr/oe 2 frz_clk 3 frz_data 4 fsel_fb2 5 pll_sel 6 ref_sel 7 clk_sel 8 clk0 9 clk1 10 clk 11 nclk 12 vdda 13 inv_clk 14 gndo 15 qc3 16 vddo 17 qc2 18 fsel_c1 19 fsel_c0 20 qc1 21 vddo 22 qc0 23 gndo 24 qsync 25 fsel_fb1 26 gndo 39 qb0 38 vddo 37 qb1 36 gndo 35 qb2 34 vddo 33 qb3 32 ext_fb 31 gndo 30 qfb 29 vdd 28 fsel_fb0 27 vco_sel 52 gndo 51 qa0 50 vddo 49 qa1 48 gndo 47 qa2 46 vddo 45 qa3 44 fsel_a0 43 fsel_a1 42 fsel_b0 41 fsel_b1 40 c6 0.1uf
15 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet reliability information table 7. ? ja vs. air flow table for a 52 lead lqfp transistor count the transistor count for 87973i-147: 8364 pin compatible with mpc973 ? ja by velocity linear feet per minute 0 200 500 single-layer pcb, jedec standard test boards 58.0c/w 47.1c/w 42.0c/w multi-layer pcb, jedec standard te st boards 42.3c/w 36.4c/w 34.0c/w note: most modern pcb designs use multi-layered boards. th e data in the second row pertains to most designs.
16 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet package outline and package dimensions package outline - y suffix for 52 lead lqfp table 8. package dimensions for 52 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: bcc all dimensions in millimeters symbol minimum nominal maximum n 52 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.22 0.38 c 0.09 0.20 d & e 12.00 basic d1 & e1 10.00 basic d2 & e2 7.80 ref. e 0.65 basic l 0.45 0.60 0.75 ? 0 7 ccc 0.10
17 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet ordering information table 9. ordering information part/order number marking package shipping packaging temperature 87973DYI-147LF ics87973di147l ?lead-free? 52 lead lqfp tray -40 ? c to 85 ? c 87973DYI-147LFt ics87973di147l ?lead- free? 52 lead lqfp tape & reel -40 ? c to 85 ? c
18 ?2016june 28, 2016 integrated device tech- june 28, 2016 87973i-147 data sheet revision history sheet rev table page description of change date b t1 t6 2 -3 4 8 11 14 updated block diagrams - added ?pu/pd? to nclk clock input. pin description table - pin number 12, nclk - added ?pullup/pulldown? in type column. ac characteristics table - f out frequency - added 10 and 12 rows. 2 row, corrected typo: maximum value from 150mhz to 250mhz. power supply filtering technique - corrected figure 2 drawing. updated wiring the differential inputs to accept single-ended levels application note. schematic example - corrected schematic layout drawing. deleted ?ics? prefix in part number throughout the datasheet. updated headers/footers. 7/27/15 b t9 17 ordering information - removed quantity from tape and reel. deleted lf note below table. product discontinuation notice - last time buy expires may 6, 2017. pdn cq-16-01. updated header and footer. 6/28/16
19 ?2016 integrated device technology, inc june 28, 2016 87973i-147 data sheet
disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not conv ey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datashee t type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 87973i-147 data sheet 20 ?2016 integrated device technology, inc june 28, 2016

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